1. Technological Field
Embodiments discussed herein relate to a solid-state imaging device and a method of driving the same and is applicable to a CMOS image sensor, for example.
2. Description of the Related Art
A so-called three-transistor complementary metal oxide semiconductor (3Tr CMOS) image sensor has heretofore been known as an example of a CMOS image sensor. A cell size for a unit cell (PIXEL) has been reduced in the CMOS image sensor of this type. The reduction in the cell size, however, leads to a reduction in area occupied by a gate electrode of an amplifying transistor, and consequently leads to a reduction in capacitance of a floating diffusion (FD) for each cell. A charge quantity Q that can be stored in the floating diffusion is expressed by Q=C×Vfd (where C denotes gate capacitance of the amplifying transistor while Vfd denotes a voltage at the floating diffusion). Accordingly, assuming that the voltage Vfd is constant, a problem arises in that the charge quantity Q that the floating diffusion can handle is reduced in proportion to a reduction in the gate capacitance C.
A method for solving this problem has been disclosed by Mabuchi et al. in the IEEE in 2004 (see, for example, “CMOS Image Sensors Comprised of Floating Diffusion Driving Pixels With Buried Photodiode”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004, which will be referred to as Non-patent Document 1 below). According to the Non-patent Document 1, a voltage at a floating diffusion is made (is boosted) to be higher than a drain voltage so that the handled charge quantity Q is increased.
Now, a conventional solid-state imaging device will be described using the Non-patent Document 1 as an example.
FIG. 4(a), from the above-mentioned Non-patent Document 1, is a potential diagram immediately after a gate of a reset transistor RST is set to a high level and the reset transistor RST is turned on (see FIG. 4A, for example). Since the reset transistor RST is turned on, a voltage at the floating diffusion FD is substantially equal to the channel potential of the reset transistor RST
Meanwhile, a voltage at a vertical signal line SIG is boosted reflecting the voltage at the floating diffusion FD. Here, boosting time is determined by the capacitance to ground of the vertical signal line SIG and current supply capability of a Load transistor. Accordingly, a relatively long time period is necessary for making the voltage at the vertical signal line SIG steady. That is, the voltage at the signal line SIG is not yet steady at a time point shown in FIG. 4(b), and is slightly higher than at a time point shown in FIG. 4(a) (see FIG. 4B, for example).
Subsequently, FIG. 4(c) is a potential diagram when the voltage at the vertical signal line SIG comes to a steady state a little while after the reset transistor RST is turned on. The floating diffusion FD in FIG. 4(c) is in a floating state after the voltage at the gate comes to substantially the same value as the channel potential of the reset transistor RST. For this reason, when the voltage at the vertical signal line SIG is changed, the floating diffusion FD has a higher voltage through a gate capacitance of an amplifying transistor AMP and the voltage at the floating diffusion FD is eventually boosted to a voltage higher than a drain voltage DRN.
Here, the change in the voltage at the floating diffusion FD in the transition from the time point in FIG. 4(b) to the potential state in FIG. 4(c) is known to be expressed by the following formula (1):
                              Δ          ⁢                                          ⁢                      V            fd                          =                                                            2                3                            ⁢                              C                amp                                                                                      2                  3                                ⁢                                  C                  amp                                            +                              C                fd                                              ⁢          Δ          ⁢                                          ⁢                      V            sig                                              (        1        )            
Here, ΔVsig is a change amount of the voltage at the vertical signal line SIG in the transition from the time point in FIG. 4(a) to the potential state in FIG. 4(c), and Camp is the gate capacitance of the amplifying transistor AMP.
Here, the reason for multiplying Camp by a coefficient “⅔” in the above formula (1) is that there is a potential difference between the drain (DRN) and the source (SIG) of the amplifying transistor AMP at the time point in FIG. 4(b) and the amplifying transistor AMP is therefore operated in a pentode region (a saturated region). For example, FIG. 4(b) illustrates how ⅔ of the gate capacitance of the amplifying transistor AMP contributes to a boosting operation.
As described above, according to the conventional solid-state imaging device, the amplifying transistor is operated in the pentode region at the time of the boosting operation. For this reason, only the two-thirds of the gate capacitance of the amplifying transistor can contribute to the boosting operation. That is to say, the conventional solid-state imaging device has a disadvantageous structure in terms of an increase in the charge amount to be stored in the floating diffusion. This disadvantage becomes more apparent when the space occupied by the gate electrode of the amplifying transistor is reduced along with the size reduction of the unit cell.